WIRELESS COMMUNICATIONS AND NETWORKS
UNIT I
WIRELESS
COMMUNICATIONS & SYSTEM FUNDAMENTALS: Introduction to wireless
communications systems, examples, comparisons & trends. Cellular
concepts-frequency reuse, strategies, interference & system capacity, trucking
& grade of service, improving coverage &capacity in cellular systems.
UNIT II
MULTIPLE
ACCESS TECHNIQUES FOR WIRELESS COMMUNICATION: FDMA, TDMA, SSMA
(FHMA/CDMA/Hybrid techniques), SDMA technique (AS applicable to wireless
communications).Packet radio access-protocols, CSMA protocols, reservation protocols,
capture effect in packet radio, capacity of cellular systems .
UNIT III
WIRELESS
NETWORKING: Introduction, differences in wireless & fixed telephone
networks, traffic routing in wireless networks –circuit switching, packet
switching X.25 protocol.
UNIT IV
Wireless
data services – cellular digital packet data(CDPD),advanced radio data
information systems ,RAM mobile data (RMD). Common channel signaling
(CCS),ISDN-Broad band ISDN & ATM ,Signaling System no .7(SS7)-protocols,
network services part, user part, signaling traffic, services &
performance.
UNIT V
MOBILE
IP AND WIRELESS APPLICATION PROTOCOL: Mobile IP Operation of mobile IP, Allocated address, Registration, Tunneling, WAP Architecture, overview, WML
scripts, WAP service, WAP session protocol, wireless transaction, Wireless data gram protocol.
UNIT VI
WIRELESS
LAN TECHNOLOGY: Infrared LANs, Spread spectrum LANs, Narrow bank microwave
LANs, IEEE 802 protocol Architecture, IEEE802 architecture and services, 802.11
medium access control, 802.11 physical layer.
UNIT VII
BLUE
TOOTH : Overview, Radio specification, Base band specification, Links manager
specification, Logical link control and adaptation protocol. Introduction to
WLL Technology.
UNIT VIII
MOBILE
DATA NETWORKS : Introduction, Data oriented CDPD Network, GPRS and higher data
rates, Short messaging service in GSM, Mobile application protocol.
TEXTBOOKS
1.
Wireless Communication and Networking – William Stallings, PHI, 2003.
2.
Wireless Communications, Principles, Practice – Theodore, S. Rappaport, PHI,
2nd Edn., 2002.
3.
Principles of Wireless Networks – Kaveh Pah Laven and P. Krishna Murthy,Pearson
Education, 2002.
REFERENCES
1. Wireless Digital Communications – Kamilo Feher, PHI, 1999.
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ANALOG AND DIGITAL IC DESIGN
UNIT-I
OPERATIONAL
AMPLIFIERS: General considerations one – state op-amps, two stage
op-amps-gains boosting stage- comparison I/P range limitations slew rate.
CURRENT
MIRRORS AND SINGLE STAGE AMPLIFIERS: simple COMS, 3JT current mirror,, Cascode
Wilson Wilder current mirrors. Common Source amplifier source follower, common
gate amplifier
NOISE: Types
of Noise – Thermal Noise-flicker noise- Noise in opamps- Noise in common source
stage
noise band
width.
UNIT-II
PHASED LOCKED
LOOP DESIGN: PLL concepts- The phase locked loop in the locked condition
Integrated circuit PLLs – phase Detector- Voltage controlled oscillator case
study: Analysis of the 560
B Monolithic
PLL.
SWITHCHED
CAPACITORS CIRCUITS: Basic Building blocks op-amps capacitors switches – non-over
lapping clocks-Basic operations and analysis-resistor equivalence of la
switched capacitor- parasitic sensitive integrator parasitic insensitive
integrators signal flow graph analysis-First order filters- switch sharing fully
differential filters – charged injectionsswitched capacitor gain circuits
parallel resistor –capacitor circuit – preset table gain circuit – other
switched capacitor circuits – full wave rectifier – peak detector sinusoidal
oscillator.
UNIT-III
LOGIC FAMILIES
& CHARACTURISTICS : COMS, TTL, ECL, logic families COMS /
TTL, interfacing comparison of logic
families.
COMBINATIONAL
LOGIC DESIGN USING VHDL: VHDL modeling for decoders, encoders,
multiplexers, comparison, adders and subtractors .
SEQUENCIAL IC
DESIGN USING VHD: VHDL modeling for larches, flip flaps, counters, shift
registers, FSMs.
UNIT-IV
DIGITAL
INTEGRADED SYSTEM BUILDING BLOCKS: Multiplexers and decoders – barrel shifters
counters digital single bit adder
MEMORIES: ROM:
Internal structure 2D decoding commercial type timing and applications
CPLD: XC 9500
series family CPLD architecture – CLB internal architecture, I/O block internal
structure .
FPGA:
Conceptual of view of FPGA – classification based on CLB internal architecture
I/O block architecture.
UNIT-V
COMPORATORS: Using an
op-amp for comparator-charge injection errors- latched comparator
NYQUIST RATE D/A
CONVERTERS: Decoder based converter resistor storing converters folded
resister string converter – Binary scale converters – Binary weighted resistor
converters – Reduced resistance ratio ladders – R-2R based converters –
Thermometer code current mode D/A converters.
NYQUIST RATE A/D
CONVERTERS: Integrating converters – successive approximation converters. DAC
based successive approximation – flash converters time interleaved A/D
converters.
REFERENCES:
1.
Analog Integrated circuit Design by David A Johns, Ken Martin,
John Wiley & Sons.
2.
Analysis and design of Analog Integrated Circuits, by Gray, Hurst
Lewis, Meyer. John Wiley & Sons.
3.
Design of Analog CMOS Integrated Circuits, Behzad Razavi, TMH
4.
Digital Integrated Circuit Design by Ken Martin, Oxford University
2000
5.
Digital Design Principles & Practices” by John F Wakerly,
Pearson Education & Xilinx Design Series, 3rd Ed.(2002)
SUGGESTED READING
1.
Ken Martin, Digital Integrated Circuit Design Oxford
University,2000.
2.
John F Wakerly, “Digital Design Principles & Practices”,
Pearson Education & Xilinx Design Series, 3rd Ed.(2002)
3.
Samir Palnitkar, “Verylog HDL-A Guide to Digital Design and Synthesis”,
Prentice Hall India, (2002)
4. Douglas J
Smith, “HDL Chip Design, a practical Guide for Designing, Synthesizing and
simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications,
(1999).
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DSP PROCESSORS AND ARCHITECTURES
UNIT I
INTRODUCTION TO
DIGITAL SIGNAL PROCESING
Introduction,
A Digital signal-processing system, The sampling process, Discrete time
sequences. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT),
Linear time-invariant systems, Digital filters, Decimation and interpolation,
Analysis and Design tool for DSP Systems MATLAB, DSP using MATLAB.
UNIT II
COMPUTATIONAL
ACCURACY IN DSP IMPLEMENTATIONS
Number formats
for signals and coefficients in DSP systems, Dynamic Range and Precision,
Sources of
error in DSP
implementations, A/D Conversion errors, DSP Computational errors, D/A
Conversion Errors, Compensating filter.
UNIT III
ARCHITECTURES
FOR PROGRAMMABLE DSP DEVICES
Basic
Architectural features, DSP Computational Building Blocks, Bus Architecture and
Memory, Data Addressing Capabilities, Address Generation Unit, Programmability
and Program Execution, Speed Issues, Features for External interfacing.
UNIT IV
EXECUTION
CONTROL AND PIPELINING
Hardware
looping, Interrupts, Stacks, Relative Branch support, Pipelining and Performance,
Pipeline Depth, Interlocking, Branching effects, Interrupt effects, Pipeline
Programming models.
UNIT V
PROGRAMMABLE
DIGITAL SIGNAL PROCESSORS
Commercial
Digital signal-processing Devices, Data Addressing modes of TMS320C54XX DSPs,
Data Addressing modes of TMS320C54XX Processors, Memory space of TMS320C54XX
Processors, Program Control, TMS320C54XX instructions and Programming, On-Chip
Peripherals, Interrupts of TMS320C54XX processors, Pipeline Operation of
TMS320C54XX Processors.
UNIT VI
IMPLEMENTATIONS
OF BASIC DSP ALGORITHMS
The
Q-notation, FIR Filters, IIR Filters, Interpolation Filters, Decimation
Filters, PID Controller, Adaptive Filters, 2-D Signal Processing.
UNIT VII
IMPLEMENTATION
OF FFT ALGORITHMS
An FFT
Algorithm for DFT Computation, A Butterfly Computation, Overflow and scaling,
Bit-Reversed index generation, An 8-Point FFT implementation on the
TMS320C54XX, Computation of the signal spectrum.
UNIT VIII
INTERFACING
MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES
Memory space
organization, External bus interfacing signals, Memory interface, Parallel I/O
interface,
Programmed
I/O, Interrupts and I/O, Direct memory access (DMA).
A Multichannel
buffered serial port (McBSP), McBSP Programming, a CODEC interface circuit,
CODEC programming,
A CODEC-DSP interface example.
TEXT BOOKS
1.
Digital Signal Processing – Avtar Singh and S. Srinivasan, Thomson
Publications, 2004.
2.
DSP Processor Fundamentals, Architectures & Features – Lapsley
et al. S. Chand & Co, 2000.
REFERENCES
1.
Digital Signal Processors, Architecture, Programming and
Applications – B. Venkata Ramani and M. Bhaskar, TMH, 2004.
2.
Digital Signal Processing – Jonatham Stein, John Wiley, 2005.
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DESIGN OF FAULT TOLERANT SYSTEMS
UNIT I
BASIC
CONCEPTS: Reliability concepts, Failure & Faults, Reliability and failure
rate, Relation between reliability and Meantime between failure,
Maintainability and Availability, Reliability of series, Parallel and
Parallel-Series combinational circuits.
UNIT II
FAULT
TOLERANT DESIGN: Basic concepts – Static, dynamic, hybrid, Triple Modular
Redundant System, Self purging redundancy, Siftout redundancy (SMR), SMR
Configuration, Use of error correcting code, Time redundancy and software
redundancy.
UNIT III
SELF
CHECKING CIRCUITS: Basic concepts of Self checking circuits, Design of Totally
Self Checking checker, Checkers using m out of n codes, Berger code, Low cost
residue code.
UNIT IV
FAIL
SAFE DESIGN: Strongly fault secure circuits, fail-safe design of sequential
circuits using partition theory and Berger code, totally self-checking PLA
design.
UNIT V
DESIGN
FOR TESTABILITY FOR COMBINATIONAL CIRCUITS: Basic concepts of testability,
controllability and observability, the Reed Muller’s expansion technique,
OR-AND-OR design, use of control and syndrome testable design.
UNIT VI
Theory
and operation of LFSR, LFSR as Signature analyzer, Multiple-input Signature
Register.
UNIT VII
DESIGN
FOR TESTABILITY FOR SEQUENTIAL CIRCUITS: Controllability and observability by
means of scan register, Storage cells for scan design, classic scan design,
Level Sensitive Scan Design (LSSD).
UNIT VIII
BUILT
IN SELF TEST: BIST concepts, Test pattern generation for BIST exhaustive
testing, Pseudorandom testing, pseudo exhaustive testing, constant weight
patterns, Generic offline BIST architecture.
TEXT BOOKS:
1. Parag K. Lala – “Fault Tolerant & Fault Testable Hardware
Design” (PHI)
2. M. Abramovili, M.A. Breues, A. D. Friedman – “Digital Systems
Testing and Testable Design” Jaico publications.
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MICROCOMPUTER SYSTEM DESIGN
Unit – I
Overview of
microcomputer systems, Historical background, Von Neumann architecture,
instruction processing, fetch and execute cycles, evolution of Intel 80x86
family of microprocessors. Architectural advances of Intel XX86 Microprocessors
series from 8086 to Pentium and Pentium Pro-Addressing Modes, Instruction sets,
Interrupt Processing.
Unit – II
Software model
of XX86 processors, Data organization, Memory Organization, Programming with
DOS and BIOS function calls.
Unit – III
8086 Processor
Architecture
CPU
Architecture – Programmer’s model, 8086 hardware details – Pinouts and Pin
function, Clock generator (8284A), Bus buffering and latching, System bus
timing - Processor Read & Write bus cycles, Ready and wait state, Minimum
and Maximum mode operations.
Unit – IV
Virtual Memory
Management: Virtual memory concept paging, segmentation, paging algorithms,
cache memory organization, Associate memory organization.
Unit –V
Memory
Interfacing
Basic
Concepts, Memory devices – ROM, SRAM, DRAM devices, Memory pin connections,
Memory read and write timing diagrams, Address decoding techniques – Random
logic (using Logic gates) decoding, block decoding (using 74LS138, 74LS139
decoders), PROM address decoding, PLD programmable decoding (using PLAs &
PALs), 8086 processor-Memory interfacing – even and odd memory banks.
Unit –VI
Basic I/O
Interfacing
Basic
Concepts, Parallel I/O, Programmed I/O, I/O port address decoding, The 8255A
Programmable Peripheral Interface(PPI), Interface examples – Keyboard matrix
interface, Printer interface and display interface, The 8254 Programmable
Interval Timer (PIT).
Interrupts &
Direct Memory Access
Basic
concepts, Interrupt driven I/O, Software & Hardware interrupts, Interrupt
vectors and vector table,
Interrupt
processing.
Unit – VII
The 8259A
Programmable Interrupt Controller (PIC), Basic DMA operation, The 8237 DMA
Controller.
Serial I/O
Communication
Basic
concepts, Asynchronous & Synchronous communication. Physical communication
standard-EIA RS232, Programmable
communication interface – Universal Asynchronous Receiver / Transmitter.
Unit – VIII
RISC &
CISC Concepts, Super scalar architecture, Pipelining, Branch Prediction,
Instruction and data caches, Floating point unit.
TEXT BOOKS
1. Barry B. Brey:
The Intel Microprocessors 8086/8088, 80188, 80386, 80486, Pentium-Pro Processor
Architecture, Programming & Interfacing (PHI) 4th
Edn.
1997.
2. John
Uffenbeck: The 8086/8088 family design, Programming & Interfacing, (PHI).
References:
1.
Microprocessor and Interfacing - Dougles V. Hall.
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Internet Protocols
Unit – 1
Introduction: Internet administration and standards. The OSI model and TCP/IP
protocol, TCP/IP Versions.
Unit – 2
Internet Protocol –
Part 1: IP addressing, different classes,
subnetting, supernetting.
Unit – 3
Delivery and routing
of IP packets, IP design, ARP and RARP.
Unit – 4
Internet Protocol –
Part III: Internet control message
protocol, message format, error reporting and query, ICMP design, Internet
group message protocol and its design, user datagram protocol, operation and
design.
Unit – 5
Transmission Control
Protocol: TCP services, flow control, error
control, connection, congestion control, TCP design and operation, routing
protocols, RIP, OSPF and BGP.
Unit – 6
BOOTP and DHCP, DNS
name space, distribution of name space, DNS resolution, types of records,
Telnet and remote login.
Unit – 7
File Transfer
Protocol, connection, communication and command processing, TFTP, simple mail
transfer protocol, addresses, mail delivery, multipurpose Internet mail
extensions. Post office protocol.
Unit – 8
Simple Network
Management Protocol, Hypertext Transfer Protocol, Next Generation IP Protocols,
IPv6.
Text Books:
1.TCP/IP Protocol
Suite – By Behrouz A. Porouzan, TMH, ed.-2000.
2. Internet Working
with TCP/IP Vol.I: Principles, Protocols and Architecture – by Douglas E.
Comes.
(PHI) - 1997.
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